As the number of logic gates in an integrated circuit (IC) increases, IC logic design becomes a disproportionately more complex process. At one time, a typical IC included only a few tens of thousands of logic gates. It is now common for an IC to include millions of logic gates. A circuit that includes millions of logic gates can be much more difficult to specify, design, and test than a smaller circuit.
One common approach to creating a large circuit is to specify the behavior of the circuit in a high-level design language such as HDL or VHDL. Computer software accepts this behavioral circuit description and generates a corresponding circuit netlist. (A “netlist” is a description of a circuit comprising a list of lower-level circuit elements, gates, or netlists and the connections (nets or nodes) between the outputs and inputs thereof.) The use of a behavioral circuit description can result in a netlist of less than perfect efficiency. Because predefined and automated procedures are followed in generating the circuit implementation, logic can sometimes be included in the netlist that is not actually utilized by the circuit.
Another common approach to creating a large circuit is to utilize pre-designed sub-circuits or modules, i.e., portions of the circuit that have previously been created and tested. Because these modules have already been designed and verified, their use can greatly improve both the design cycle time and the speed and accuracy of the resulting circuit. However, the module designers are typically attempting to satisfy a wide user base. Therefore, they tend to include in the modules whatever capabilities might be of use to their potential customers. Module users who do not need or desire some of these capabilities can find themselves with a circuit netlist that includes logic elements not used in their target application.
To accommodate these unused logic elements, some IC design software includes a “trimming” feature, whereby logic that drives unused nodes is automatically trimmed from the circuit. In other words, if a node has a source but no destination, the logic driving the node is removed from the circuit. Sometimes nodes without a destination are actually necessary in a design, such as when deliberately mimicking the loading on another node. Therefore, this type of software can include some mechanism for marking logic to be retained even if the output node has no destination. However, in general, it is desirable to eliminate unused logic, as smaller circuits lead to lower costs for both manufacturers and end users of the circuit.
Verifying the functionality and timing of large and complex ICs is also no small task. To test the logical behavior of the design, the circuit description (e.g., the behavioral description or netlist) is typically carefully simulated. Using a computer to simulate the behavior of the circuit, high and low values are assigned to selected nodes (e.g., input nodes), and the values of various other nodes are monitored and compared to expected data. Discrepancies are investigated, and their causes are found and corrected. Some simulators can also mimic the timing to be expected from a circuit after manufacture, based on a detailed circuit description that includes transistor sizes and device models.
Additional testing is performed after the IC has been manufactured. Even if the logical design of the circuit is flawless, the manufacturing process can produce flawed devices, e.g., devices including shorts between metal traces on the die, or opens creating gaps in what should be a single trace. Therefore, a set of test vectors (i.e., one or more test patterns) are applied to the IC. Ideally, the complete set of test patterns ensures that each node in the entire circuit can toggle successfully in both directions between high and low values.
The term “fault coverage” is used to denote the percentage of nodes in the IC that are actually tested by a set of test patterns. For example, the term can refer to the percentage of nodes that make both high-to-low and low-to-high transitions when subjected to the set of test patterns. The term can also be used to refer to the percentage of nodes that assume both high and low values. Ideally, the fault coverage for a set of test patterns is one hundred percent (100%).
Test time can contribute significantly to the cost of IC production. Therefore, there is value in minimizing the length of time required to run the full set of test patterns, while still achieving one hundred percent fault coverage. Hence, software tools have been developed that allow the assessment of test patterns for the amount of fault coverage they provide.
A fault coverage simulator (fault simulator) accepts a circuit description (e.g., a netlist for an entire IC) and a set of test patterns to be evaluated. The circuit is then simulated using the test patterns to supply the input stimulus. For the purpose of fault analysis, it is not necessary to compare the actual values computed for the output nodes with the expected values. Instead, as the simulation progresses, the fault simulator monitors and records each node in the circuit, and keeps track of which nodes actually switch and in which direction (i.e., high-to-low and/or low-to-high). The fault simulator provides the resulting record to the user, who can then alter the test patterns to appropriately toggle the reported untested nodes, and reassess the test patterns for improved fault coverage. The goal is to achieve one hundred percent fault coverage for the circuit from a minimal set of input vectors for the design.
Therefore, it is desirable to provide both efficient circuit implementations and efficient test patterns providing one hundred percent fault coverage for the circuit implementations.